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Publikationen

Channel-length-independent hot-carrier degradation in analog p-MOS operation

R. Thewes, M. Brox, G. Tempel, W. Weber, and K. Goser

Volume: 13 pp. 590-592, 1992.


Hot-carrier degradation of p-MOSFET's in analog operation: the relevance of the channel-length-independent drain conductance degradation

R. Thewes, M. Brox, G. Tempel, W. Weber, and K. Goser

R. Thewes, M. Brox, G. Tempel, W. Weber, and K. Goser. Hot-carrier degradation of p-MOSFET's in analog operation: the relevance of the channel-length-independent drain conductance degradation. Tech. Digest International Electron Device Meeting (IEDM) 1992. San Francisco, CA


Hot-carrier stress effects of p-MOSFETs: physical effects relevant for circuit operation

W. Weber, M. Brox, A. v. Schwerin, and R. Thewes

Volume: 22 (1-4) pp. 253-260, 1993. Amsterdam, The Netherlands, The Netherlands


Mechanisms of hot-carrier degradation of analog device parameters in n-MOSFETs

R. Thewes, W. Weber, and K. Goser

pp. 85-88, 1993. Conference Location : Grenoble


Evaluation of the hot-carrier-induced offset voltage of differential pairs in analog circuits

R. Thewes, M. Kivi, K. Goser, and W. Weber

pp. 127-130, 1994.


Characterization and model of the hot-carrier-induced offset voltage of analog CMOS differential stages

R. Thewes, K. Goser, and W. Weber

pp. 303-306, 1994. Conference Location : San Francisco, CA, USA


Hot-hole-induced negative oxide charges in n-MOSFETs

W. Weber, M. Brox, R. Thewes, and N. S. Saks

pp. 311-314, 1994. Conference Location : San Francisco, CA


Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling

S. A. Kühn, M. B. Kleiner, R. Thewes, and W. Weber

1 pp. 37-40, 1995. Conference Location: Seattle, WA


Performance evaluation of interface architectures for electromagnetic signal transmission in 3-dimensional ICs

S. A. Kühn, R. Thewes, M. B. Kleiner, and W. Weber

pp. 350-353, 1995. Conference Location: Lille, France


Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages

M. Eisele, J. Berthold, R. Thewes, E. Wohlrab, D. Schmitt-Landsiedel, and W. Weber

pp. 67-70, 1995. Washington, DC


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